Enhanced Low Power CMOS Current Comparator using Diode Free Adiabatic (DFAL) Technique

Authors:P.GREESHMA, ER. NULI NAMASSIVAYA

0664-0667

Implementation of Low Power and High Speed Single Precession Floating Point Multiplier using Kogge-Stone Adder and Dadda Multiplier

Authors:SMARANIKA ROUT, DR. S. K. MANDAL

0668-0674

Data Hiding using RDH Algorithm with Contrast Enhancement

Authors:GAYATHRI GUNUKULA, RAVI BABU KANCHARLA

0675-0678

Advancing of Power Management in Home with Smart Grid Technology And Sensor Nose

Authors:SHAIK NAGULMEERA NURJAHAN, M KEZIA ARUNA JYOTHI

0679-0681

Low Power Comparator Design for SAR-ADC

Authors:CHANDNI SARGAIYA, R. S. GAMAD

0682-0685

32-Bit Razor Based Dynamic Voltage Scaling using Multiprecision Multiplier

Authors:KAJA SUKANYA, R. RAJESH KUMAR, K. HARIBABU

0686-0689

Reversable Gated Vedic Multiplier Low Power Design

Authors:S. MADHAVI

0690-0696

Efficient Adaptive Hold Logic Reliable Multiplier using Variable Latency Design

Authors:KOMATIKUNTLA RAMESH, DR.M.L RAVICHANDRA

0697-0701

Design and Anaysis of Shift Register using Pulse Triggered Latches

Authors:NOSSAM NEELUFER, S.RAMANJI NAIK

0702-0706

High Performance and Implementation of 64-Bit MAC Units and Their Delay Comparison for Binary Multipliers

Authors:CHILAKALA JAYANTH REDDY, A. PRASAD

0707-0711